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| HMS87C5216 HMS87C5216 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR UR(Universal Remocon) & WIRELESS KEYBOARD 1. OVERVIEW 1.1 Description The HMS87C5216 is an advanced CMOS 8-bit microcontroller with 16K bytes of ROM. The device is one of GMS800 family. The MagnaChip Semicon HMS87C5216 is a powerful microcontroller which provides a highly flexible and cost effective solution to many UR & Keyboard applications. The HMS87C5216 provides the following standard features: 16K bytes of ROM, 320 bytes of RAM, 8-bit timer/ counter, on-chip oscillator,clock circuitry and RC wake up function. 4 chanel ADC, In addition, the HMS87C5216 Series supports power saving modes to reduce power consumption Device name ROM Size EPROM Size RAM Size Operatind Voltage Package 28 SOP 40 PDIP 44 PLCC 44 QFP HMS87C5216 - 16K byte 320bytes 2.0 ~ 5.5V 1.2 Features * Instruction Cycle Time: - 1us at 4MHz * Programmable I/O pins * 8 Interrupt sources * Nested Interrupt control is available. - External input: 2 - Keyscan input - Basic Interval Timer - Watchdog timer - Timer : 3 * Power On Reset * Power saving Operation Modes - STOP - SLEEP * Low Voltage Detection Circuit * Watch Dog Timer Auto Start (During 1second after Power on Reset) * 4 CHANEL ADC * RC TIMER WAKE UP 28 PIN INPUT OUTPUT I/O 2 2 22 40 PIN 2 2 34 44 PIN 2 2 38 * Operating Voltage - 2.0 ~ 5.5 V @ 4MHz * Timer - Timer / Counter ......... 16Bit * 1ch ........ 16Bit * 2ch - Basic Interval Timer ...... 8Bit * 1ch - Watch Dog Timer ............ 6Bit * 1ch SEP. 2004 Ver 1.01 HMS87C5216 1.3 Development Tools The HMS87C5216 and HMS87C5216 are supported by a fullfeatured macro assembler, an in-circuit emulator CHOICEDrTM. In Circuit Emulators Assembler OTP Writer OTP Devices CHOICE-Dr. HME Macro Assembler Single Writer : Sigma 4-Gang Writer : Dr.Gang HMS87C5216 SEP. 2004 Ver 1.01 HMS87C5216 2. BLOCK DIAGRAM PSW ALU Accumulator Stack Pointer Data Memory PC RESET System controller System Clock Controller Timing generator 8-bit Basic Interval Timer Interrupt Controller Program Memory Data Table Xin Xout Clock Generator Instruction Decoder Watch-dog Key Wake up 8-bit A/D Converter 8-bit Timer/ Counter Carrier Generator RC Watch Timer LVD/POR VDD VSS Power Supply R0 R1 R2 R3 R4 R00 / KS0 R01 / KS1 R02 / KS2 R03 / KS3 R04 / KS4 R05 / KS5 R06 / KS6 R07 / KS7 R10 / INT1 R11 / INT2 R12 / T0 R13 / T1 R14 / AN0 R15 / AN1 R16 / AN2 R17 / AN3 R20 R21 R22 R23 R24 /T2 R25 / EC0 R26 R27 REMOUT R30 R31 R32 R33 R34 R35 R36 R37 R40 R41 R42 R43 R44 SEP. 2004 Ver 1.01 HMS87C5216 3. PIN ASSIGNMENT VSS R22 R21 R20 R33 R32 R42 R31 42 R30 41 R23 44 43 R01 R02 R03 R04 R05 R06 R07 VDD XOUT XIN R10 R11 R12 R13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R00 REMOUT R25 R24 R23 R22 R21 R20 VSS R17 R16 R15 R14 RESETB 40 6 5 4 3 2 1 R17 R24 R25 R26 R27 R43 REMOUT R00 R01 R02 R03 R04 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 R16 R40 R15 R14 RESETB R45 R41 R13 R12 R11 R10 28PIN 44PLCC 34 33 32 31 30 29 R05 18 R06 19 R07 20 R34 21 R35 22 R44 23 VDD 24 R36 25 R37 26 R31 25 XOUT 27 R30 24 R22 R21 R20 R33 R01 R02 R03 R04 R05 R06 R07 R34 R35 VDD R36 R37 XOUT XIN R10 R11 R12 R13 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 39 38 37 36 35 34 33 32 31 30 28 27 26 25 R27 R26 R25 R24 R23 R22 R21 R20 R33 R32 R31 R30 R17 R16 R24 R25 R26 R27 R43 REMOUT R00 R01 R02 R03 R04 34 35 36 37 38 39 40 41 42 43 44 26 VSS 33 R23 28 R32 27 R42 32 31 30 29 23 R17 R00 1 40 REMOUT XIN 28 22 R16 21 R40 20 R15 19 R14 18 40PDIP RESETB R45 R41 R13 R12 R11 R10 44QFP 17 16 15 14 13 12 29 VSS 24 R40 XOUT 10 22 21 R14 RESETB XIN 11 1 2 3 4 5 6 7 8 9 23 R15 R05 R06 R34 R36 R41 20 VDD R07 R35 R44 R37 SEP. 2004 Ver 1.01 HMS87C5216 4. PIN DIAGRAM SEP. 2004 Ver 1.01 HMS87C5216 2.075 2.045 0.600 BSC 0.550 0.530 0.140 0.120 0.200 max. MIN 0.015 0.022 0.015 0.065 0.045 0.100 BSC 0.012 0.008 SEP. 2004 Ver 1.01 HMS87C5216 SEP. 2004 Ver 1.01 HMS87C5216 5. PIN FUNCTION VDD: Supply voltage. VSS: Circuit ground. RESET: Reset the MCU. XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. XOUT: Output from the inverting oscillator amplifier. R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R1 serves the functions of the various following special features. Port pin R10 R11 R12 R13 R14 R15 R16 R17 Alternate function INT1 (External Interrupt input 1) INT2 (External Interrupt input 2) T0 (Timer / Counter inpit 0) T1 (Timer / Counter inpit 1) AN0 (ADC input 0) AN1 (ADC input 1) AN2 (ADC input 2) AN3 (ADC input 3) R20~R22, R30~R37 : R2 & R3 is a 8-bit CMOS bidirectional I/ O port. Each pins 1 or 0 written to the their Port Direction Register can be used as outputs or inputs. In addition, R2 serves the functions of the various following special features. Port pin R24 R25 Alternate function T2 (Timer / Counter inpit 2) /EC (Event Counter input ) R40~R43 : R4 is 1-bit CMOS bidirectional I/O port. This pin 1 or 0 written to the its Port Direction Register can be used as outputs or inputs. SEP. 2004 Ver 1.01 HMS87C5216 6. PIN Name XIN XOUT R00/KS0 R01/KS1 R02/KS2 R03/KS3 R04/KS4 R05/KS5 R06/KS6 R07/KS7 R10/KS8/INT1 R11/KS9/INT2 R12/KS10/T0 R13/KS11/T1 R14/KS12/AN0 R15/KS13/AN1 R16/KS14/AN2 R17/KS15/AN3 I/O I,O # 2 Main Clock Input,Output Each bit of the port can be individually configured as an input or an output by user software Push-pull output CMOS input with pull-up resistor (can be programmable) Programmable Key Scan Input or Open drain output Pull-ups are automatically disabled at output mode Each bit of the port can be individually configured as an input or an output by user software Push-pull output CMOS input with pull-up resistor (can be programmable) Programmable Key Scan Input or Open drain output Direct Driving of LED (N-TR) Pull-ups are automatically disabled at output mode R1[7:4] is High Driving Capability R1[7:4] is Schmitt Trigger Input. Each bit of the port can be individually configured as an input or an output by user software Push-pull output CMOS input with pull-up resistor (can be programmable) Programmable Open drain output Direct Driving of LED (N-TR) Pull-ups are automatically disabled at output mode Resetb Pin Remocon Output Power Supply Ground Description @Reset Oscillation @STOP L, L I/O 8 Input State of before STOP I/O 8 Input State of before STOP R2[3:0] R24/T2 R25/EC0 R2[7:6] R3[7:0] R4[5:0] RESETB REMOUT VDD VSS I/O 22 Input State of before STOP I O - 1 1 1 1 L L VDD VSS H L VDD VSS SEP. 2004 Ver 1.01 HMS87C5216 7. PORT STRUCTURES * RESET ll-Up Resistor Selection Open Drain Selection Data Register Direction Selection RD Port0 Bus MUX Noise Canceller KS_EN[7:0] VD 7:0] ll-Up Resistor Selection VD Open Drain Selection Data Register Direction Selection RD Port1 Bus MUX Noise Canceller KS_EN[9:8] Noise Canceller 8 .INT2 _EN,INT2_EN SEP. 2004 Ver 1.01 HMS87C5216 * Xin, Xout SEP. 2004 Ver 1.01 HMS87C5216 l-Up Resistor Selection Open Drain Selection ata Register Direction Selection 0 Bus MUX Noise Canceller KS_EN[11:10] RD Port1 VD ,10 l-Up Resistor Selection VD Open Drain Selection ata Register Direction Selection RD Port1 Bus MUX Noise Canceller 5:12] EN[15:12] 3:0] _EN & nnel Selection l-Up Resistor Selection Open Drain Selection ata Register Direction Selection RD Port2 Bus MUX VD SEP. 2004 Ver 1.01 HMS87C5216 * RA0/EC0 SEP. 2004 Ver 1.01 HMS87C5216 * RA1/AN1 ~ RA7/AN7 ll-Up Resistor Selection VD Open Drain Selection Data Register Direction Selection RD Port2 Bus MUX VDD VDD PAD XIN Noise Canceller _EN STOP Am ll-Up Resistor Selection Open Drain Selection Data Register Direction Selection RD Port2,3,4 Bus MUX VD VDD VDD REMOUT PA SEP. 2004 Ver 1.01 HMS87C5216 8. ELECTRICAL CHARACTERISTICS (HMS87C5216/GMS81C1408) 8.1 Absolute Maximum Ratings Supply voltage......................................................-0.3 to +7.0 V Storage Temperature ..........................................-40 to +125 C aximum current out of VSS pin ................................... TBD mA Maximum current into VDD pin .................................. TBD mA Maximum current sunk by (IOL per I/O Pin) .............. TBD mA Maximum output current sourced by (IOH per I/O Pin) ..................................................................................... TBD mA Maximum current (IOL) ............................................. TBDmA Maximum current (IOH)............................................. TBDmA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 8.2 Recommended Operating Conditions Parameter Supply Voltage Operating Frequency Operating Temperature Symbol VDD fXIN TOPR Condition fXIN=4MHz VDD=2.0~5.5V VDD=2.0~5.5V Specifications Min. 2.0 1 -20 Max. 5.5 4 85 Unit V MHz C 8.3 A/D Converter Characteristics (TA=25 C, VSS=0V, VDD=3.072V @fXIN =4MHz) Specifications Min. VSS-0.3 fXIN=4MHz Typ. 1.0 1.0 1.0 0.5 0.25 1.0 Max. VDD+0.3 200 2.0 2.0 2.0 1.5 0.5 1.5 30 Parameter Analog Input Voltage Range Current Following Between AVdd and AVss Overall Accuracy Non-Linearity Error Differential Non-Linearity Error Zero Offset Error Full Scale Error Gain Error Conversion Time Symbol VAIN IAVdd NACC NNLE NDNLE NZOE NFSE NNLE TCONV Condition - Unit V uA LSB LSB LSB LSB LSB LSB uS 8.4 DC Electrical Characteristics (TA=-20~85 C for HMS87C5216/1408 or TA=-40~85 C for HMS87C5216E/1408E, VDD=2.2~5.5V, VSS=0V), Specifications Min. 0.8 VDD Typ. Max. VDD Parameter Input High Voltage Symbol VIH1 Pin XIN, RESET Condition Unit V SEP. 2004 Ver 1.01 HMS87C5216 Parameter Symbol VIH1 VIH2 Pin RESET,XIN,INT1,IN T2,EC0,R1<7:4> R0,R1,R2,R3,R4 RESET,XIN,INT1,IN T2,EC0,R1<7:4> R0,R1,R2,R3,R4 R0,R1,R2,R3,R4 RESETB R0,R1,R2,R3,R4 R0,R1<3:0>,R2,R3, R4 R1<7:0>, XOUT R0,R1<3:0>,R2,R3, R4 XOUT R0,R1,R2,R3,R4 R0,R1,R2,R3,R4 REMOUT REMOUT R0,R1,R2,R3,R4 RESETB Hysteresis Input1 Main OSC Feedback Resistor Active Mode Sleep Mode Stop Mode,Osc Stop Condition Specifications Min. 0.8VDD 0.7VDD 0 Typ. 100 4.0 2.4 2.0 1.0 5.0 3.0 Max. VDD VDD 0.2VDD 0.3VDD 1.0 -1.0 0.8 0.5 1.0 -1.0 -5 3 200 1.0 10 6 3.0 2.0 30 25 Unit V V V V A A V V V V V A A mA mA V Input High Voltage Input Low Voltage Input High Leakage Current Input Low Leakage Current VIL1 VIL2 IIH IIL VOH1 0 VIH=VDD VIL=0V Ioh1=-0.8mA,VDD=3V Ioh2=-2.0mA,VDD=3V VDD-0.4 VDD-0.4 VDD-0.5 - Output High Voltage VOH2 VOH3 Ioh3=-50uA,VDD=3V Output Low Voltage Output High Leakage Current Output Low Leakage Current Output High Current Output Low Current Input Pull-up Hysteresis Feed Back Resistor VOL1 VOL2 IIOHL IIOLL IOH IOL IP | VT | RF! IOL=5mA,VDD=3V IOL=50uA,VDD=3V VOH=VDD VOL=0V VDD=3V,VOH=2.0V VDD=3V,VOL=1.0V VDD=3V VDD=5V VDD=3.0V, fXIN=4MHz VDD=4.0V VDD=2.0V VDD=4.0V VDD=2.0V VDD=4.0V VDD=2.0V -20 -0.5 50 0.5 0.2 - IDD Supply Currnet Isleep Istop mA mA mA mA A A SEP. 2004 Ver 1.01 HMS87C5216 8.5 AC Characteristics (TA=-20~85 C for HMS87C5216/1408 or TA=-40~85 C for HMS87C5216E/1408E, VDD=5V10%, VSS=0V) Specifications Min. 1 0.5 80 2 8 2 0 20 20 Typ. Max. 4 2.0 20 Parameter Operating Frequency Systemp Clock Cycle Time Oscillation Stabilizing Time(4MHz) External Clock "H" or "L" Pulse Width External Clock Transition Time Interrupt Input Pulse Width RESETB Input Pulse "L" Width Event Couter Input "H" or "L" Pulse Width Event Couter Transition Time Symbol fMCP tSYS tMST! tCPW tRCP,tFCP tlW tRST tTCW tREC,tFEC Pins XIN XIN, XOUT XIN XIN INT1,INT2 RESETB ECo ECo Unit MHz uS mS nS nS tSYS tSYS tSYS nS 1/fMCP tCPW tCPW XIN 0.8VDD 0.2VDD tRCP tFCP tIW tIW INT1 INT2 0.8VDD 0.2VDD tRST RESETB 0.2VDD tECW tECW EC0 0.8VDD 0.2VDD tREC tFEC Figure 8-1 Timing Chart SEP. 2004 Ver 1.01 HMS87C5216 9. MEMORY ORGANIZATION The HMS87C5216 have separate address spaces for Program memory and Data Memory. Program memory can only be read, not written to. It can be up to 16K bytes of Program memory. Data memory can be read and written to up to 320 bytes including the stack area. 9.1 Registers This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register. A X Y SP PCH PCL PSW ACCUMULATOR X REGISTER Y REGISTER STACK POINTER PROGRAM COUNTER PROGRAM STATUS WORD 15 1 identifies the location in the stack to be accessed (save or restore). Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 100H to 17FH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of "17FH" is used. Stack Address (100H ~17FH) 8 7 SP 0 Hardware fixed Figure 9-1 Configuration of Registers Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below. Y Y A Note: The Stack Pointer must be initialized by software because its value is undefined after RESET. Example: To initialize the SP LDX #07FH TXSP ; SP 7FH Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 9-3. It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result. A Two 8-bit Registers can be used as a "YA" 16-bit Register Figure 9-2 Configuration of YA 16-bit Register X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer SEP. 2004 Ver 1.01 HMS87C5216 MSB PSW NEGATIVE FLAG OVERFLOW FLAG SELECT DIRECT PAGE FLAG BRK FLAG LSB N V G B H I Z C RESET VALUE: 00H CARRY FLAG RECEIVES CARRY OUT ZERO FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS Figure 9-3 PSW (Program Status Word) Register [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address. [Overflow flag V] This flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH) or 128(80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag. [Direct page flag G] This flag assigns RAM page for direct addressing mode. In the direct addressing mode, addressing area is from zero page 00 to FF when this flag is 0. If it is set to 1, addressing area is 1 page. It is set by instruction and cleared by CLRG. SEP. 2004 Ver 1.01 HMS87C5216 9.2 Program Memory A 16-bit program counter is capable of addressing up to 64K bytes, but these devices have 16K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Figure 9-4, shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 9-5. As shown in Figure 9-4, each area is assigned a fixed location in Program Memory. Program Memory area contains the user program. Example: Usage of TCALL LDA #5 TCALL 0FH : : ;1BYTE INSTRUCTION ;INSTEAD OF 3 BYTES ;NORMAL CALL C000H ; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0 RET ; FUNC_B: LDA LRG1 2 RET ; ;TABLE CALL ADD. AREA ; ORG 0FFC0H DW FUNC_A DW FUNC_B 1 ;TCALL ADDRESS AREA F000H PROGRAM MEMORY FEFFH FF00H FFC0H FFDFH FFE0H FFFFH TCALL AREA INTERRUPT VECTOR AREA PCALL AREA The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte interval: 0FFF8H and 0FFF9H for External Interrupt 1, 0FFFAH and 0FFFBH for External Interrupt 0, etc. As for the area from 0FF00H to 0FFFFH, if any area of them is not going to be used, its service location is available as general purpose Program Memory. Address 0FFE0H E2 E4 E6 E8 EA EC EE F0 F2 F4 F6 F8 FA FC FE Vector Area Memory ADC Interrupt Vector Area RC WT Interrupt Vector Area BIT Interrupt Vector Area WDT Interrupt Vector Area Timer/Counter 2 Interrupt Vector Area Timer/Counter 1 Interrupt Vector Area Timer/Counter 0 Interrupt Vector Area EXT2 Interrupt Vector Area EXT1 Interrupt Vector Area KEY SCAN Interrupt Vector Area RESET Vector Area NOTE: "-" means reserved area. Figure 9-4 Program Memory Map Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2H for TCALL14, etc., as shown in Figure 9-6. Figure 9-5 Interrupt Vector Area SEP. 2004 Ver 1.01 HMS87C5216 Address 0FFC0H C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF Program Memory TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK * NOTE: * means that the BRK software interrupt is using same address with TCALL0. Address 0FF00H PCALL Area Memory PCALL Area (256 Bytes) 0FFFFH Figure 9-6 PCALL and TCALL Memory Area TCALLn 4A TCALL 4 PCALLrel 4F35 PCALL 35H 4A 01001010 4F 35 0F125H ~ ~ NEXT ~ ~ Reverse PC: 11111111 11010110 FH FH DH 6H ~ ~ 0FF00H 0FF35H 0FFFFH NEXT ~ ~ 0FF00H 0FFD6H 0FFD7H 0FFFFH 25 F1 A A SEP. 2004 Ver 1.01 HMS87C5216 Example: The usage software example of Vector address and the initialize part. ORG DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW ORG 0FFE0H NOT_USED; (0FFEO) NOT_USED; (0FFE2) ADC_INT; (0FFE4) A/D Interface RC_WT_INT; (0FFE6) RC WAKE UP Timer BIT_INT; (0FFE8) BIT Timer WDT_INT; (0FFEA) WDT NOT_USED; (0FFEC) TMR2_INT; (0FFEE) Timer-2 TMR1_INT; (0FFF0) Timer-1 TMR0_INT; (0FFF2) Timer-0 NOT_USED; (0FFF4) EXT2_INT; (0FFF6) External2 EXT1_INT; (0FFF8) External1 KEY_SCAN; (0FFFA) Key Scan NOT_USED; (0FFFC) RESET; (0FFFE) Reset 0F000H ;******************************************** ; MAIN PROGRAM * ;******************************************* ; RESET: DI ;Disable All Interrupts LDX #0 RAM_CLR: LDA #0;RAM Clear(!0000H->!00BFH) STA {X}+ CMPX #0C0H BNE RAM_CLR ; LDX #07FH;Stack Pointer Initialize TXSP ; CALL INITIAL; ; LDM R1, #0;Normal Port A LDM R1DD,#1000_0010B;Normal Port Direction LDM R2, #0;Normal Port B LDM R2DD,#1000_0010B;Normal Port Direction : : : : SEP. 2004 Ver 1.01 HMS87C5216 9.3 Data Memory Figure 9-7 shows the internal Data Memory space available. Data Memory is divided into two groups, a user RAM (including Stack) and control registers. 0000H Address Address 0C0H 0C1H 0C2H 0C3H 0C4H 0C5H 0C6H 0C7H 0C7H 0C8H 0C9H 0CAH 0CBH 0CCH 0CDH 0CEH 0CFH 0D0H 0D1H 0D2H 0D3H 0D4H 0D5H 0D5H 0D6H 0D6H 0D7H 0D8H 0D8H 0D9H 0D9H 0DAH 0DCH 0DDH 0DEH 0DFH 0E0H 0E1H 0E4H 0E5H 0E6H 0E7H 0E8H 0EEH 0EFH Symbol Symbol R0 R0DR R1 R1DR R2 R2DR TMR1 CKCTLR BITR WDTR PSR RCWTR IESR IENL IRQL IENH IRQH TM0 TM1 TM2 T0HMD T0HLD T0MC T0LMD T0LC T0LLD T1HD T1C T1LD T2C T2D TM01 KSR0 KSR1 R10D R2OD R3OD R4OD R0OD R3 R3DR R4 R4DR TMR2 LVDR R/W R/W R/W W R/W W R/W W W W R W W W W R/W R/W R/W R/W R/W R/W R/W W W R W R W W R W R W R/W W W W W W W W R/W W R/W W R R RESET Value RESET Value Undefined 0000_0000 Undefined 0000_0000 Undefined 0000_0000 0000_0000 --11_0111 0000_0000 -000_1111 --00_0000 ----_1000 --00_00--000_-0--000_-0-000-_000000-_0000000_0000 0000_-000 ---0_0000 Undefined Undefined 0000_0000 Undefined 0000_0000 Undefined Undefined 0000_0000 Undefined 0000_0000 Undefined 0000_0000 00000_000 0000_0000 0000_0000 0000_0000 0000_0000 --00_0000 0000_0000 Undefined 0000_0000 Undefined --00_0000 0000_0000 ---_-00- Addressing mode Addressing mode byte, bit1 byte2 byte, bit byte byte, bit byte byte byte byte byte byte byte,bit byte,bit byte,bit byte,bit byte,bit byte,bot byte, bit byte, bit byte, bit byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte,bit byte byte byte byte,bit byte byte,bit byte byte byte USER MEMORY PAGE0 00BFH 00C0H 00FFH 0100H CONTROL REGISTERS USER MEMORY (including STACK) PAGE2 017FH Figure 9-7 Data Memory Map User Memory The HMS87C5216 has 330 x 8 bits for the user memory (RAM). Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and I/O ports. The control registers are in address range of 0C0H to 0FFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section. Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction. Example; To write at CKCTLR LDM CKCTLR,#09H ;Divide ratio /16 Note: Several names are given at same address. Refer to- Table 9-1 Control Registers SEP. 2004 Ver 1.01 HMS87C5216 0F0H 0F4H 0F5H 0F6H 0F7H 0F8H 0F9H 0FAH 0FBH 0FCH SMR ADMR ADDR KRL0 KRL1 R0PU R1PU R2PU R3PU R4PU W R/W R W W W W W W W ----_---0 -000_0001 Undefined 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 0000_0000 --00_0000 byte byte, bit byte byte byte byte byte byte byte byte below table. Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Table 9-1 Control Registers 1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit. SEP. 2004 Ver 1.01 HMS87C5216 9.4 Addressing Mode The HMS87C5216 and GMS81C1408 uses six addressing modes; (3) Direct Page Addressing dp In this mode, a address is specified within direct page. Example; C535 LDA 35H ;A RAM[35H] * Register addressing * Immediate addressing * Direct page addressing * Absolute addressing * Indexed addressing * Register-indirect addressing 0035H data A ~ ~ ~ ~ 0F550H C5 35 0F551H data A (1) Register Addressing Register addressing accesses the A, X, Y, C and PSW. (2) Immediate Addressing #imm In this mode, second byte (operand) is accessed as a data immediately. Example: 0435 ADC #35H MEMORY (4) Absolute Addressing !abs Absolute addressing sets corresponding memory data to Data, i.e. second byte(Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. 04 35 A+35H+C A ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example; 0735F0 ADC !0F035H ;A ROM[0F035H] E45535 LDM 35H,#55H 0F035H data A ~ ~ ~ ~ 0035H data data 55H 0F100H 0F101H 0F102H 07 35 F0 A+data+C A address: 0F035 0F100H 0F101H 0F102H ~ ~ E4 55 35 ~ ~ A SEP. 2004 Ver 1.01 HMS87C5216 The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H. 983500 INC !0035H ;A RAM[035H] X indexed direct page, auto increment{X}+ In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; X=35H DB LDA {X}+ 0035H data A ~ ~ ~ ~ 0F100H 0F101H 0F102H 98 35 00 A data+1 data 35H data A ~ ~ data A address: 0035 ~ ~ DB 36H X (5) Indexed Addressing X indexed direct page (no offset) {X} In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H D4 LDA {X} ;ACC RAM[X]. X indexed direct page (8 bit offset) dp+X This address value is the second byte (Operand) of command plus the data of X-register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; X=015H C645 LDA 45H+X 15H data A ~ ~ data A ~ ~ 0E550H D4 5AH data A ~ ~ 0E550H 0E551H C6 45 ~ ~ A 45H+15H=5AH data A SEP. 2004 Ver 1.01 HMS87C5216 Y indexed direct page (8 bit offset) dp+Y This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. 3F35 JMP [35H] Y indexed absolute !abs+Y Sets the value of 16-bit absolute address plus Y-register data as Memory. This addressing mode can specify memory in whole area. Example; Y=55H D500FA LDA !0FA00H+Y 35H 36H 0A E3 ~ ~ 0E30AH NEXT ~ ~ A jump to address 0E30AH ~ ~ 0FA00H 3F 35 ~ ~ 0F100H 0F101H 0F102H D5 00 FA 0FA00H+55H=0FA55H ~ ~ 0FA55H data ~ ~ A A data A X indexed indirect [dp+X] Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plus X-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; X=10H 1625 ADC [25H+X] (6) Indirect Addressing Direct page indirect [dp] Assigns data address to use for accomplishing command which sets memory data(or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL Example; 0E005H 35H 36H 05 E0 ~ ~ data ~A ~ 0E005H ~ ~ 25 + X(10) = 35H ~ ~ 0FA00H 16 25 A A + data + C A SEP. 2004 Ver 1.01 HMS87C5216 Y indexed indirect [dp]+Y Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct page plus Yregister data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; Y=10H 1725 ADC [25H]+Y Absolute indirect [!abs] The program jumps to address specified by 16-bit absolute address. JMP Example; 1F25E0 JMP [!0C025H] PROGRAM MEMORY 25H 26H 05 E0 0E025H 0E026H 25 E7 ~ ~ 0E015H data ~ ~ A 0E005H + Y(10) = 0E015H ~ ~ ~ ~ NEXT A jump to address 0E30AH ~ ~ 0E725H ~ ~ 0FA00H 17 25 ~ ~ 0FA00H 1F 25 E0 ~ ~ A A + data + C A SEP. 2004 Ver 1.01 HMS87C5216 10. I/O PORTS The GMS87C5216 has 38 I/O ports which are PORT0(8 I/O), PORT1 (8 I/O), PORT2 (8 I/O), PORT3 (8 I/O), PORT4 (6 I/O). Pull-up resistor of each port can be selectable by program. Each port contains data direction register which controls I/O and data register which stores port data (1) R0 I/O Data Direction Register (R0DD) R0 I/O Data Direction Register (R0DD) is 8-bit register, and can assign input state or output state to each bit. If R0DD is 1, port R0 is in the output state, and if 0, it is in the input state. R0DD is write-only register. Since R0DD is initialized as 00 h in reset state, the whole port R0 becomes input state. 10.1 R0 Ports R0 is an 8-bit CMOS bidirectional I/O port (address 0C0H). Each I/O pin can independently used as an input or an output through the R0DD register (address 0C1H). R0 has internal pull-ups that is independently connected or disconnected by R0PC. The control registers for R0 are shown below. (2) R0 Data Register (R0) R0 data register (R0) is 8-bit register to store data of port R0. When set as the output state by R0DD, and data is written in R0, data is outputted into R0 pin. When set as the input state, input state of pin is read. The initial value of R0 is unknown in reset state. (3) R0 Open drain Assign Register (R0ODC) R0 Data Register (R/W) R0 ADDRESS : 0C0H RESET VALUE : Undefined R07 R06 R05 R04 R03 R02 R01 R00 R0 Direction Register (W) R0DD ADDRESS : 0C1H RESET VALUE : 00H R0 Open Drain Assign Register (R0ODC) is 8bit register, and can assign R0 port as open drain output port each bit, if corresponding port is selected as output. If R0ODC is selected as 1, port R0 is open drain output, and if selected as 0, it is push-pull output. R0ODC is write-only register and initialized as 00 h in reset state. (4) R0 Pull-up Resistor Control Register (R0PC) Port Direction 0: Input 1: Output R0 Pull-up Selection Register (W) R0PC ADDRESS :0F8H RESET VALUE : 00H R0 pull-up resistor control register (R0PC) is 8-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. If R0PC is selected as 1, pull-up ia disabled and if selected as 0, it is enabled. R0PC is write-only register and initialized as 00 h in reset state. The pull-up is automatically disabled, if corresponding port is selected as output. Pull-up select 1: Without pull-up 0: With pull-up 10.2 R1 Ports R1 is an 8-bit CMOS bidirectional I/O port (address 0C2H). Each I/O pin can independently used as an input or an output through the R1DD register (address 0C3H). R1 has internal pull-ups that is independently connected or disconnected by register R1PC. The control registers for R1 are shown below. R0 Open drain Assign Register (W) ADDRESS :0E4H RESET VALUE : 00H R0ODC Open drain select 0: Push-pull 1: Open drain SEP. 2004 Ver 1.01 HMS87C5216 R1 Data Register (R/W) R1 ADDRESS : 0C2H RESET VALUE : Undefined bit of PMR1 acts as port R1 selection mode, and when set as 1, it becomes function selection mode. PMR1 is write-only register and initialized as 00 h in reset state. Therefore, becomes Port selection mode. Port R1 can be I/ O port by manipulating each R1DD bit, if corresponding PMR1 bit is selected as 0. R17 R16 R15 R14 R13 R12 R11 R10 R1 Direction Register (W) R1DD ADDRESS : 0C3H RESET VALUE : 00H Port Direction 0: Input 1: Output R1 Pull-up Selection Register (W) R1PC Pull-up select 1: Without pull-up 0: With pull-up ADDRESS : 0F9H RESET VALUE : 00H Pin Name EC0 PMR1 Selection Mode Remarks 0 1 0 1 0 1 0 1 0 1 0 1 R25(I/O) EC0(I) R24(I/O) T2(O) R13 (I/O) T1(O) R12 (I/O) T0(O) R11 (I/O) INT2(I) R10(I/O) INT1(I) EVENT COUNT0 TIMER2 TIMER1 TIMER0 EXT INT2 EXT INT1 T2 R1 Open drain Assign Register (W) ADDRESS : 0DEH RESET VALUE : 00H P1ODC Open drain select 0: Push-pull 1: Open drain T1 T0 R1 Port Mode Register (W) PMR1 ADDRESS : 0C9H RESET VALUE : 00H INT2 Mode select 0: Port R1 selection 1: Function selection INT1 Table 10-1 Selection mode of PMR1 (4) R1 Pull-up Resistor Control Register (R1PC) R1 pull-up resistor control register (R1PC) is 8-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. If R1PC is selected as 1, pull-up ia disabled and if selected as 0, it is enabled. R1PC is write-only register and initialized as 00 h in reset state. The pull-up is automatically disabled, if corresponding port is selected as output. (1) R1 I/O Data Direction Register (R1DD) R1 I/O Data Direction Register (R1DD) is 8-bit register, and can assign input state or output state to each bit. If R1DD is 1, port R1 is in the output state, and if 0, it is in the input state. R1DD is write-only register. Since R1DD is initialized as 00 h in reset state, the whole port R1 becomes input state. (2) R1 Data Register (R1) R1 data register (R1) is 8-bit register to store data of port R1. When set as the output state by R1DD, and data is written in R1, data is outputted into R1 pin. When set as the input state, input state of pin is read. The initial value of R1 is unknown in reset state. 10.3 R2 Port R2 is an 8-bit CMOS bidirectional I/O port (address 0C4H). Each I/O pin can independently used as an input or an output through the R2DD register (address 0C5H). R2 has internal pujll-ups that is independently connected or disconnected by R2PC (address 0FAH). The control registers for R2 are shown as below. (3) R1 Mode Register (PMR1) R1 Port Mode Register (PMR1) is 8-bit register, and can assign the selection mode for each bit. When set as 0, corresponding SEP. 2004 Ver 1.01 HMS87C5216 R2 Data Register (R/W) R2 ADDRESS : 0C4H RESET VALUE : Undefined assign input state or output state to each bit. If R2DD is 1, port R2 is in the output state, and if 0, it is in the input state. R2DD is write-only register. Since R2DD is initialized as 00 h in reset state, the whole port R2 becomes input state. R27 R26 R25 R24 R23 R22 R21 R20 (2) R2 Data Register (R2) R2 Direction Register (W) R2DD Port Direction 0: Input 1: Output R2 Pull-up Selection Register (W) R2PC Pull-up select 1: Without pull-up 0: With pull-up ADDRESS :0FAH RESET VALUE : 00H ADDRESS : 0C5H RESET VALUE : 00H R2 data register (R2) is 8-bit register to store data of port R2. When set as the output state by R2DD, and data is written in R2, data is outputted into R2 pin. When set as the input state, input state of pin is read. The initial value of R2 is unknown in reset state. (3) R2 Open drain Assign Register (R2ODC) R2 Open Drain Assign Register (R2ODC) is 8bit register, and can assign R2 port as open drain output port each bit, if corresponding port is selected as output. If R2ODC is selected as 1, port R2 is open drain output, and if selected as 0, it is push-pull output. R2ODC is write-only register and initialized as 00 h in reset state. R2 Open drain Assign Register (W) ADDRESS :0DFH RESET VALUE : 00H R2ODC Open drain select 0: Push-pull 1: Open drain (4) R2 Pull-up Resistor Control Register (R2PC) R2 pull-up resistor control register (R2PC) is 8-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. If R2PC is selected as 1, pull-up ia disabled and if selected as 0, it is enabled. R2PC is write-only register and initialized as 00 h in reset state. The pull-up is automatically disabled, if corresponding port is selected as output. (1) R2 I/O Data Direction Register (R2DD) R2 I/O Data Direction Register (R2DD) is 8-bit register, and can SEP. 2004 Ver 1.01 HMS87C5216 R3 Port R3 is an 8-bit CMOS bidirectional I/O port (address 0E5H). Each I/O pin can independently used as an input or an output through the R3DD register (address 0E6H). R3 has internal pull-ups that is independently connected or disconnected by R3PC (address 0FBH). The control registers for R3 are shown as below. (1) R3 I/O Data Direction Register (R3DD) R3 I/O Data Direction Register (R3DD) is 8-bit register, and can assign input state or output state to each bit. If R3DD is 1, port R3 is in the output state, and if 0, it is in the input state. R3DD is write-only register. Since R3DD is initialized as 00 h in reset state, the whole port R3 becomes input state. (2) R3 Data Register (R3) R3 data register (R3) is 8-bit register to store data of port R3. When set as the output state by R3DD, and data is written in R3, data is outputted into R3 pin. When set as the input state, input state of pin is read. The initial value of R3 is unknown in reset state. R3 Data Register (R/W) R3 ADDRESS : 0E5H RESET VALUE : Undefined R37 R36 R35 R34 R33 R32 R31 R30 R3 Direction Register (W) R3DD ADDRESS : 0E6H RESET VALUE : 00H (3) R3 Open drain Assign Register (R3ODC) R3 Open Drain Assign Register (R3ODC) is 8bit register, and can assign R3 port as open drain output port each bit, if corresponding port is selected as output. If R3ODC is selected as 1, port R3 is open drain output, and if selected as 0, it is push-pull output. R3ODC is write-only register and initialized as 00 h in reset state. Port Direction 0: Input 1: Output R3 Pull-up Selection Register (W) R3PC Pull-up select 1: Without pull-up 0: With pull-up ADDRESS :0FBH RESET VALUE : 00H (4) R3 Pull-up Resistor Control Register (R3PC) R3 pull-up resistor control register (R3PC) is 8-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. If R3PC is selected as 1, pull-up ia disabled and if selected as 0, it is enabled. R3PC is write-only register and initialized as 00 h in reset state. The pull-up is automatically disabled, if corresponding port is selected as output. R3 Open drain Assign Register (W) ADDRESS :0E0H RESET VALUE : 00H R3ODC Open drain select 0: Push-pull 1: Open drain SEP. 2004 Ver 1.01 HMS87C5216 R4 Port R4 is an 1-bit CMOS bidirectional I/O port (address 0E7H). Each I/O pin can independently used as an input or an output through the R4DD register (address 0E8H). R3 has internal pull-ups that is independently connected or disconnected by R4PC (address 0FCH). The control registers for R4 are shown as below. (1) R4 I/O Data Direction Register (R4DD) R4 I/O Data Direction Register (R4DD) is 1-bit register, and can assign input state or output state to each bit. If R4DD is 1, port R4 is in the output state, and if 0, it is in the input state. R4DD is write-only register. Since R4DD is initialized as 00 h in reset state, the whole port R4 becomes input state. (2) R4 Data Register (R4) R4 data register (R4) is 1-bit register to store data of port R4. When set as the output state by R4DD, and data is written in R4, data is outputted into R4 pin. When set as the input state, input state of pin is read. The initial value of R4 is unknown in reset state. R4 Data Register (R/W) R4 ADDRESS : 0E7H RESET VALUE : Undefined R44 R43 R42 R41 R40 R4 Direction Register (W) R4DD ADDRESS : 0E8H RESET VALUE : 00H (3) R4 Open drain Assign Register (R4ODC) R4 Open Drain Assign Register (R4ODC) is 1-bit register, and can assign R4 port as open drain output port each bit, if corresponding port is selected as output. If R4ODC is selected as 1, port R4 is open drain output, and if selected as 0, it is pushpull output. R4ODC is write-only register and initialized as 00 h in reset state. Port Direction 0: Input 1: Output R4 Pull-up Selection Register (W) R4PC Pull-up select 1: Without pull-up 0: With pull-up ADDRESS :0FCH RESET VALUE : 00H (4) R4 Pull-up Resistor Control Register (R4PC) R4 pull-up resistor control register (R4PC) is 1-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. If R4PC is selected as 1, pull-up ia disabled and if selected as 0, it is enabled. R4PC is write-only register and initialized as 00 h in reset state. The pull-up is automatically disabled, if corresponding port is selected as output. R4 Open drain Assign Register (W) ADDRESS :0E1H RESET VALUE : 00H R4ODC Open drain select 0: Push-pull 1: Open drain SEP. 2004 Ver 1.01 HMS87C5216 11. CLOCK GENERATOR Clock generating circuit consists of Clock Pulse Generator (C.P.G), Prescaler, Basic Interval Timer (B.I.T) and Watch Dog Timer. The clock applied to the Xin pin divided by two is used as the internal system clock. OSC Circuit fex C.P.G fcpu Internal System Clock PRESCALER IFBIT PS1 ENPCK 8 MUX 0 B.I.T (8) 7 0 WDT (6) 9 5 WDTCL BTCL 3 Peripheral COMPARATOR WDTON 6 WDTR 0 Internal Data Bus 5 6 6 IFWDT CKCTLR 0 1 2 3 4 5 To Reset Circuit Figure 11-1 Block Diagram of Clock Generator Prescaler consists of 12-bit binary counter. The clock supplied from oscillation circuit is input to prescaler (fex). The divided output from each bit of prescaler is provided to peripheral hardware. fex PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 ENPCK B.I.T fcpu PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 Peripheral Figure 11-2 Block diagram of Prescaler SEP. 2004 Ver 1.01 HMS87C5216 fex (MHz) ps 0 ps 1 ps 2 ps 3 ps 4 ps 5 ps 6 ps 7 ps 8 ps 9 ps 10 ps 11 ps 12 4 MHz frequency 4 MHz 2 MHz 1 MHz 500 KHz 250 KHz 125 KHz 62.5 KHz 31.25 KHz 15.63 KHz 7.183 KHz 3.906 KHz 1.953 KHz 0.976 KHz period 250 ns 500 ns 1 us 2 us 4 us 8 us 16 us 32 us 64 us 128 us 256 us 512 us 1024 us frequency 2 MHz 1 MHz 500 KHz 250 KHz 125 KHz 62.5 KHz 31.25 KHz 15.63 KHz 7.183 KHz 3.906 KHz 1.953 KHz 0.976 KHz 0.488 KHz 2 MHz period 500 ns 1 us 2 us 4 us 8 us 16 us 32 us 64 us 128 us 256 us 512 us 1024 us 2048 us Table 11-1 ps output period lock to peripheral hardware can be stopped by bit4 (ENPCK) of CKCTLR Register. ENPCK is set to 1 in reset state. SEP. 2004 Ver 1.01 HMS87C5216 12. Timer 12.1 Basic Interval Timer The GMS81C5016/24/32 has one 8-bit Basic Interval Timer that is free-run and can not stop. Block diagram is shown in Figure 121. The Basic Interval Timer generates the time base for key scanning, watchdog timer counting, and etc. It also provides a Basic interval timer interrupt (IFBIT). As the count overflow from FFH to 00H, this overflow causes the interrupt to be generated. -8bit binary counter -Use the bit output of prescaler as input to secure the oscillation stabilization time after power-on -Secures the oscillation stabilization time in standby mode (stop mode) release -Contents of B.I.T can be read -Provides the clock for watch dog timer. DATA BUS - - WDTON ENPCK BTCL BTS2 BTS1 BTS0 CKCTLR PS3 PS4 PS5 PS6 MUX PS7 PS8 PS9 PS10 DATA BUS BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BITR BIT7 IFBIT Figure 12-1 Block Diagram of Basic Interval Timer (1) Control of B.I.T The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in Figure 12-2. If bit3(BTCL) of CKCTLR is set to 1, B.I.T is cleared, and then, after one machine cycle, BTCL becomes 0, and B.I.T starts counting. BTCL is set to 0 in reset state. SEP. 2004 Ver 1.01 HMS87C5216 7 CKCTLR Clock Control Register WDTON ENPCK BTCL BTS2 BTS1 0 BTS0 W <00C7 h> - BTCL 0 1 Periphral clock free-run Automatically cleared, after one cycle Figure 12-2 BTCL mode of B.I.T (2) Input clock selection of B.I.T The input clock of B.I.T can be selected from the prescaler within a range of 2us to 256us by clock input selection bits (BTS2~BTS0). (at fex = 4MHz). In reset state, or power on reset, BTS2=1, BTS1=1, BTS0=1 to secure the longest oscillation stabilization time. B.I.T can generate the wide range of basic interval time interrupt request (IFBIT) by selecting prescaler output. Interrupt interval can be selected to kinds of interval time as shown in Figure 12-3. 7 CKCTLR Clock Control Register WDTON ENPCK BTCL BTS2 BTS1 0 BTS0 W <00C7 h> - BTS2 0 0 0 0 1 1 1 1 BTS1 0 0 1 1 0 0 1 1 BTS0 0 1 0 1 0 1 0 1 B.I.T. Input clock PS3 (2us) PS4 (4us) PS5 (8us) PS6 (16us) PS7 (32us) PS8 (64us) PS9 (128us) PS10 (256us) Standby release time 512 us 1,024 us 2,048 us 4,096 us 8,192 us 16,384 us 32,768 us 65,536 us Figure 12-3 Basic Interval Timer Interrupt Time (3) Reading Basic Interval Timer By reading of the Basic Interval Timer Register (BITR), we can read counter value of B.I.T. Because B.I.T can be cleared or read, the spending time up to maximum 65.5ms can be available. B.I.T is read-only register. If B.I.T register is written, then CKCTLR register with same address is written. SEP. 2004 Ver 1.01 HMS87C5216 7 BITR BIT7 BIT6 Basic Interval Timer Register BIT5 BIT4 BIT3 BIT2 BIT1 0 BIT0 R <00C7 h> 12.2 Timer0, Timer1, Timer2 (1) Timer Operation Mode Timer consists of 16bit binary counter Timer0 (T0), 8bit binary Timer1 (T1), Timer2 (T2), Timer Data Register, Timer Mode Register (TM01, TM0, TM1, TM2) and control circuit. Timer Data Register Consists of Timer0 High-MSB Data Register (T0HMD), Timer0 High-LSB Data Register (T0HLD), Timer0 Low-MSB Data Register (T0LMD), Timer0 Low-LSB Data Register (T0LLD), Timer1 High Data Register (T1HD), Timer1 Low Data Register (T1LD), Timer2 Data Register (T2DR). Any of the PS0 ~ PS5, PS11 and external event input EC can be selected as clock source for T0. Any of the PS0 ~ PS3, PS7 ~ PS10 can be selected as clock T1. Any of the PS5 ~ PS12 can be selected as clock source for T2. * Relevant Port Mode Register (PMR1 : 00C9 h) value should be assigned for event counter, Timer0 - 16-bit Interval Timer - 16-bit Event Counter - 16-bit Input Capture - 16-bit rectangular-wave output - 8-bit Interval Timer - 8-bit rectangular-wave output - 8-bit Interval Timer - 8-bit rectangular-wave output - Modulo-N Mode Timer1 Timer2 - Single/Modulo-N Mode - Timer Output Initial Value Setting - Timer0~Timer1 combination Logic Output - One Interrupt Generating Every 2nd Counter Overflow SEP. 2004 Ver 1.01 HMS87C5216 EC / R14 TIMER0 (16 BIT) Polarity Selection T0 OUT / R17 INT2 / R12 (Capture Signal) EDGE Selection 16 16 8 T0HMD T1HD 8 TIMER1 (8 BIT) T0HLD T1LD 8 8 T0LMD T0LLD 8 Tout LOGIC 8 REMOUT T1 OUT / R16 TIMER2 (8 BIT) T2 OUT / R15 T2DR Figure 12-4 Timer / Counter Block diagram (2) Function of Timer & Counter fex = 4MHz 16bit Timer (T0) Resolution (CK) PS0 ( 0.25 us) PS1 ( 0. 5 us) PS2 ( PS3 ( PS4 ( PS5 ( 1 us) 2 us) 4 us) 8 us) Max. Count 16,384 us 32,768 us 65,536 us 131,072 us 262,144 us 524,288 us 33,554,432 us 8bit Timer (T1) Resolution (CK) PS0 ( 0.25 us) PS1 ( PS2 ( PS3 ( PS7 ( PS8 ( 0.5 us) 1 us) 2 us) 32 us) 64 us) Max. Count 64 us 128 us 256 us 512us 8,192 us 16,384 us 32,768 us 65,536 us 8bit Timer (T2) Resolution (CK) PS5 ( PS6 ( PS7 ( PS8 ( 8 us) 16 us) 32 us) 64 us) Max. Count 2.048 us 4,096 us 8,192 us 16,384 us 32,768 us 65,536 us 131,072 us 262,144 us PS9 ( 128 us) PS10 ( 256 us) PS11 ( 512 us) PS12 (1,024 us) PS11 ( 512 us) EC PS9 ( 128 us) PS10 ( 256 us) SEP. 2004 Ver 1.01 HMS87C5216 Internal Data Bus R/W <00D0 h> TM0 7 6 5 4 3 2 1 0 <00D5 h> TIMER0 H COUNT REG <00D6 h> <00D3 h> TIMER0 HM DATA REG <00D4 h> <00D5 h> TIMER0 LM DATA REG <00D6 h> TIMER0 L COUNT REG TIMER0 HL DATA REG TIMER0 LL DATA REG DATA READ SINGLE/ MODULO-N SELECTION 16 16 MUX 16 PS0 PS1 PS2 PS3 PS4 PS5 PS11 EC D E L A INT2 EDGE SELECTION Y M U X MUX CK T0 COUNTER (16 BIT) IFT0 Clear Int. Gen. T0INT OUTPUT GEN. T0 OUT Figure 12-5 Block Diagram of Timer0 SEP. 2004 Ver 1.01 HMS87C5216 Internal Data Bus <00D8 h> TIMER1 COUNT REG <00D7 h> TIMER1 H DATA REG <00D8 h> <00D1h> TM1 7 6 5 4 3 X 2 1 0 R/W TIMER1 L DATA REG SINGLE/ MODULO-N SELECTION OUTPUT GEN. PS0 PS1 PS2 PS3 PS7 PS8 PS9 PS10 IFT1 MUX CK T1 COUNTER (8 BIT) Int. Gen. T1INT OUTPUT GEN. T1OUT Figure 12-6 Block Diagram of Timer1 Internal Data Bus <00D9 h> TIMER2 COUNT REG <00D9 h> TIMER2 DATA REG <00D2 h> TM2 7 6 5 4 3 2 1 0 R/W PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 OUTPUT GEN. T2 OUT MUX CK T2 COUNTER (8 BIT) IFT2 SEP. 2004 Ver 1.01 HMS87C5216 Figure 12-7 Block Diagram of Timer2 7 TM01 TOUTS TOUTB Timer0 / Timer1 Mode Register T0OUTP T0INIT T1INIT TOUT1 0 TOUT0 R / W <00DA h> TOUT0 0 0 1 1 T1INIT 0 1 T0INIT 0 1 T0OUTP 0 1 TOUTB 0 1 TOUTS 0 1 TOUT1 0 1 0 1 TOUT LOGIC AND of T0 OUTPUT and T1 OUTPUT NAND of T0 OUTPUT and T1 OUTPUT OR of T0 OUTPUT and T1 OUTPUT NOR of T0 OUTPUT and T1 OUTPUT Timer1 Output Initial Value Timer1 output low Timer1 output high Timer0 Output Initial Value Timer0 Output Low Timer0 Output High T0OUT Polarity Selection T0OUT polarity equal to TOUT logic input signal T0OUT polarity reverse to TOUT logic input signal REMOUT Port Bit Control REMOUT output low REMOUT output high REMOUT Port Output Selection (TOUT logic or TOUTB) Bit (TOUTB) output through REMOUT TOUT logic output through REMOUT Figure 12-8 Timer0 / Timer1 Mode Register SEP. 2004 Ver 1.01 HMS87C5216 7 TM0 CAP0 T0ST Timer0 Mode Register T0CN T0MOD T0IFS T0SL2 T0SL1 0 T0SL0 R / W <00D0 h> T0SL2 0 0 0 0 1 1 1 1 T0IFS 0 1 T0MOD 0 1 T0CN 0 1 T0ST 0 1 CAP0 0 1 T0SL1 0 0 1 1 0 0 1 1 T0SL0 0 1 0 1 0 1 0 1 Input clock selection PS0 (250ns) PS1 (500ns) PS2 ( PS3 ( PS4 ( PS5 ( 1us) 2us) 4us) 8us) * Notes PS11 (512us) EC Event Counter Timer0 Interrupt Selection Interrupt every counter overflow Interrupt every 2nd counter overflow Timer0 Single/Modulo-N Selection Modulo-N Single Timer0 Counter Continuation/Pause Control Count pause Count contination Timer0 Start/Stop Control Timer0 Stop Timer Start after clear Timer0 Interrupt Selection Timer/Counter Input capture * * PS1 : not supporting input capture. Figure 12-9 Timer0 Mode Register SEP. 2004 Ver 1.01 HMS87C5216 7 TM1 T1ST T1CN Timer1 Mode Register T1MOD T1IFS T1SL2 T1SL1 0 T1SL0 R / W <00D1 h> T1SL2 0 0 0 0 1 1 1 1 T1IFS 0 1 T1MOD 0 1 T1CN 0 1 T1ST 0 1 T1SL1 0 0 1 1 0 0 1 1 T1SL0 0 1 0 1 0 1 0 1 Input clock selection PS0 (250ns) PS1 (500ns) PS2 ( PS3 ( 1us) 2us) PS7 ( 32us) PS8 ( 64us) PS9 (128us) PS10 (256us) Timer1 Interrupt Selection Interrupt every counter overflow Interrupt every 2nd counter overflow Timer1 Single/Modulo-N Selection Modulo-N Single Timer1 Counter Continuation/Pause Control Count pause Count contination Timer1 Start/Stop Control Timer1 Stop Timer1 Start after clear Figure 12-10 Timer1 Mode Register SEP. 2004 Ver 1.01 HMS87C5216 7 TM2 - Timer2 Mode Register T2ST T2CN T2SL2 T2SL1 0 T2SL0 R / W <00D2 h> T2SL2 0 0 0 0 1 1 1 1 T2CN 0 1 T2ST 0 1 T2SL1 0 0 1 1 0 0 1 1 T2SL0 0 1 0 1 0 1 0 1 Input clock selection PS5 PS6 PS7 PS8 PS9 ( 8us) ( 16us) ( 32us) ( 64us) ( 128us) PS10 ( 256us) PS11 ( 512us) PS12 (1024us) Timer2 Counter Continuation/Pause Control Count pause Count contination Timer2 Start/Stop Control Timer2 Stop Timer2 Start after clear Figure 12-11 Timer2 Mode Register 7 IEDS - External Interrupt Signal Edge Selection Register IED2H IED2L IED1H IED1L - 0 W <00CB h> IED*H 0 0 1 1 IED*L 0 1 0 1 INT* Falling Edge Selection Rising Edge Selection Both Edge Selection Figure 12-12 External Interrupt Signal Edge Selection Register SEP. 2004 Ver 1.01 HMS87C5216 (3) Timer0, Timer1 TIMER0 and TIMER1 have an up-counter. When value of the up-counter reaches the content of Timer Data Register (TDR), the up-counter is cleared to 00 h, and interrupt (IFT0, IFT1) is occured at the next clock. T0 Data Registers Value T0 Value Concurrence Concurrence Concurrence 0 CLEAR INTERRUPT CLEAR INTERRUPT CLEAR INTERRUPT IFT0 Interval period Figure 12-13 Operatiion of Timer0 For Timer0, the internal clock (PS) and the external clock (EC) can be selected as counter clock. But Timer1 and Timer2 use only internal clock. As internal clock. Timer0 can be used as internaltimer which period is determined by Timer Data Register (TDR). Chosen as external clock, Timer0 executes as event-counter. The counter execution of Timer0 and Timer1 is controlled by T0CN, T0ST, CAP0, T1CN, T1ST, of Timer Mode Register TM0 and TM1. T0CN, T1CN are used to stop and start Timer0 and Timer1 without clearing the counter. T0ST, T1ST is used to clear the counter. For clearing and starting the counter, T0ST or T1ST should be temporarily set to 0 and then set to 1. T0CN, T1CN, T0ST and T1ST should be set 1, when Timer counting-up. Controlling of CAP0 enables Timer0 as input capture. By programming of CAP0 to 1, the period of signal from INT2 can be measured and then, event counter value for INT2 can be read. During counting-up, value of counter can be read. Timer execution is stopped by the reset signal (RESET = L) Note: In the process of reading 16-bit Timer Data, first read the upper 8-bit data. Then read the lower 8-bit data, and read the upper 8-bit data again. If the earlier read upper 8-bit data are matched with the later read upper 8-bit data, read 16-bit data are correct. If not, caution should be taken in the selection of upper 8-bit data. (Example) 1) Upper 8-bit Read 0A 0A 2) Lower 8-bit Read FF 01 3) Upper 8-bit Read 0B 0B ===================== 0AFF 0B01 SEP. 2004 Ver 1.01 HMS87C5216 T0 Data Register Value T0 Value Concurrence Concurrence 0 CLEAR INTERRUPT CLEAR INTERRUPT IFT0 T0ST 0 1 Clear & Start T0CN 0 1 Counter Stop Count Clear & Count Stop Count Clear & Start continue Figure 12-14 Start/Stop operation of Timer0 T3 T2 T1 T0 INT2 Figure 12-15 Input capture operation of Timer0 * Single/Modulo-N Mode Timer0 (Timer1) can select initial (T0INIT, T1INIT of TM01) output level of Timer Output port. If initial level is L, LowData Register value of Timer Data Register is transferred to comparator and T0OUT (T1OUT) is to be Low, if initial level is High? High -Data Register is transferred and to be High. Single Mode can be set by Mode Select bit (T0MOD, T1MOD) of SEP. 2004 Ver 1.01 HMS87C5216 Timer Mode Register (TM0, TM1) to 1 When used as Single Mode, Timer counts up and compares with value of Data Register. If the result is same, Time Out interrupt occurs and level of Timer Output port toggle, then counter stops as reset state. When used as Modulo-N Mode, T0MOD (T1MOD) should be set 0. Counter counts up until the value of Data Register and occurs Time-out interrupt. The level of Timer Output port toggle and repeats process of counting the value which is selected in Data Register. During Modulo-N Mode, If interrupt select bit (T0IFS, T1IFS) of Mode Register is 0, Interrupt occurs on every Time-out. If it is 1, Interrupt occurs every second time-out. Note: (*note. Timer Output is toggled whenever time out happen) [ Single Mode ] 8bit / 16bit counting Timer Enable initial. value toggle. Timer-output toggle. interrupt occurs. count stop. [ Modulo-N Mode ] 8bit / 16bit counting Timer Enable initial. value toggle. Timer-Output Toggle. Int occurs (IFS = 1) Each 2nd time out. Int occurs (IFS = 0) When Time out. Figure 12-16 Operation Diagram for Single/Modulo-N Mode (4) Timer 2 Timer2 operates as a up-counter. The content of T2DR are compared with the contents of up-counter. If a match is found. Timer2 interrupt (IFT2) is generated and the up-counter is cleared to 00 h. Therefore, Timer2 executes as a interval timer. Interrupt period is determined by the count source clock for the Timer2 and content of T2DR. When T2ST is set to 1, count value of Timer 2 is cleared and starts counting-up. For clearing and starting the Timer2. T2ST have to set to 1 after set to 0. In order to write a value directly into the T2DR, T2ST should be set to 0. Count value of Timer2 can be read at any time. SEP. 2004 Ver 1.01 HMS87C5216 T2 Data Registers Value T2 Value Concurrence Concurrence Concurrence 0 CLEAR INTERRUPT CLEAR INTERRUPT CLEAR INTERRUPT IFT0 Interval period Figure 12-17 Operation of Timer2 T2 Data Register Value T2 Value Concurrence Concurrence 0 CLEAR INTERRUPT CLEAR INTERRUPT IFT2 T2ST count stop by 0 count start clear by 1 Counter Count up Count Stop Count continue Count up after clear Figure 12-18 Start/Stop of Timer2 SEP. 2004 Ver 1.01 HMS87C5216 13. INTERRUPTS The GMS81C5016/24/32 interrupt circuits consist of Interrupt Mode Register (MOD), Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Priority circuit and Master enable flag ("I" flag of PSW). 8 interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 13-1. The GMS81C5016/24/32 contains 8 interrupt sources; 3 externals and 5 internals. Nested interrupt services with priority control is also possible. Software interrupt is non-maskable interrupt, the others are all maskable interrupts. - 8 interrupt source (2Ext, 3Timer, BIT, WDT and Key Scan) - 8 interrupt vector - Nested interrupt control is possible - Programmable interrupt mode - Hardware accept mode - Software selection accept mode - Read and write of interrupt request flag are possible. - In interrupt accept, request flag is automatically cleared. Internal Data Bus 0 IENL 7 0 IENH 7 0 IMOD 7 - KSCN INT1 INT2 IFT0 IFT1 IFT2 IFWDT IFBIT KSCNR INT1R INT2R T0R T1R T2R WDTR BITR IRQ Standby Mode Release BRK PRIORITY CONTROL INT. VECTOR ADDR. Figure 13-1 Block Diagram of Interrupt 13.1 Interrupt priority and sources. Each interrupt vector is independent and has its own priority. Software interrupt (BRK) is also available. Interrupt source classification is shown in Table 13-1. SEP. 2004 Ver 1.01 HMS87C5216 Mask non-maskable Priority 0 1 2 Interrupt Source RST (RESET pin) KSCNR (Key Scan) INT1R (External Interrupt1) INT2R (External Interrupt2) T0R (Timer0) T1R (Timer1) T2R (Timer2) WDTR (Watctdog Timer) BITR (Basic Interval Timer) BRK instruction INT Vector High FFFF FFFB FFF9 FFF7 FFF3 FFF1 FFEF FFE9 FFE7 FFDF INT Vector Low FFFE FFFA FFF8 FFF6 FFF2 FFF0 FFEE FFE8 FFE6 FFDE Hardwar e Interrupt maskable 3 4 5 6 7 - - Table 13-1 Interrupt Priority & Source 13.2 INTERRUPT CONTROL REGISTER I flag of PSW is a interrupt mask enable flag. When I flag = 0, all interrupts become disable. When I flag = 1, interrupts can be selectively enabled and disabled by contents of corresponding Interrupt Enable Register. When interrupt is occured, interrupt request flag is set, and Interrupt request is detected at the edge of interrupt signal. The accepted interrupt request flag is automatically cleared during interrupt cycle process. The interrupt request flag maintains 1 until the interrupt is accepted or is cleared in program. In reset state, interrupt request flag register (IRQH, IRQL) is cleared to 0. It is possible to read the state of interrupt register and to mainpulate the contents of register and to generate interrupt. (Refer to software interrupt). IENL IENH IRQL IRQH R/W <00CCh> KSCNE KSCNE WDTR INT1E WDTR INT1R BITE INT2E BITE INT2R T0E T0R T1E T1R T2E T2R - R/W <00CEh> R/W <00CDh> R/W <00CFh> IENL : INTERRUPT ENABLE REGISTER LOW IENH : INTERRUPT ENABLE REGISTER HIGH IRQL : INTERRUPT REQUEST REGISTER LOW IRQH : INTERRUPT REQUEST REGISTER HIGH 13.3 INTERRUPT ACCEPT MODE The interrupt priority order is determined by bit (IM1, IM0) of IMOD register. SEP. 2004 Ver 1.01 HMS87C5216 7 IMOD - Interrupt Mode Register IM1 IM0 IP3 IP2 IP1 0 IP0 R/W <00CA h> Assigning by interrupt accept mode bit IM1 0 0 1 IM0 0 1 * fixed by hardware changeable by IP3~ IP0 Interrupt is inhibited Priority (1) Selection of Interrupt by IP3-IP0 The condition allow for accepting interrupt is set state of the interrupt mask enable flag and the interrupt enable bit must be 1. In Reset state, these IP3 IP0 registers become all 0. IP3 0 0 0 0 0 0 0 1 1 1 1 1 IP2 0 0 0 1 1 1 1 0 0 0 0 1 IP1 0 1 1 0 0 1 1 0 0 1 1 0 IP0 1 0 1 0 1 0 1 0 1 0 1 0 Selection Interrupt KSCNR (Key Scan) INT1R (External interrupt 1) INT2R (External interrupt 2) Reserved T0R (Timer 0) T1R (Timer 1) T2R (Timer 2) Reserved Reserved WDTR (Watch Dog Timer) BITR (Basic Interval Timer) Reserved Table 13-1 Interrupt Selection by IP3 - IP0 (2) Interrupt Timing CLOCK A command before interrupt interrupt process step SYNC Interrupt Request Sampling Figure 13-2 Interrupt Enable Accept Timing *Interrupt Request sampling time SEP. 2004 Ver 1.01 HMS87C5216 -Maximum 12 machine cycle (When execute DIV instruction) -Minimum 0 machine cycle *Interrupt preprocess step is 8 machine cycle *Interrupt overhead -Maximum 1 + 12 + 8 = 21 machine cycle -Minimum 1 + 0 + 8 = 9 machine cycle (3) The valid timing after executing Interrupt control instructions I flag is valid just after executing of EI/DI on the contrary. Interrupt Enable register is valid one instruction after controlling interrupt Enable Register. 13.4 INTERRUPT PROCESSING SEQUENCE When an interrupt is accepted, the on-going process is stopped and the interrupt service routine is executed. After the interrupt service routine is completed it is necessary to restore everything to the state before the interrupt occured.As soon as an interrupt is accepted, the content of the program counter and PSW are savedin the stack area. At the same time, the content of the vector address corresponding to the accepted interrupt, which is in the interrupt vector table, enters into the program counter and interrupt service is executed. In order to execute the interrupt service routine, it is necessary to write the jump addresses in the vector table (FFE0 h ~ FFFF h) corresponding to each interrupt * Interrupt Processing Step 1) Store upper byte of Program Counter, SP <= SP 2) Store lower byte of Program Counter, SP <= SP - 1 3) Store Program Status Word, SP <= SP - 2 4) After resetting of I-flag, clear accepted Interrupt Request Flag. (Set B-flag for BRK Instruction) 5) Call Interrupt service routine clock Interrupt Process Step ISR *1 SYNC R/W internal addr bus internal data bus internal READ internal WRITE *2 PC SP SP-1 SP-2 LVA *3 HVA new PC OP CODE OP CODE PCH PCL PSW L vector H vector *1 ISR *2 LVA *3 HVA : Interrupt Service Routine : Low Vector Address : High Vector Address Figure 13-3 Interrupt Procesing Step Timing 13.5 SOFTWARE INTERRUPT (Interrupt by Break (BRK) Instruction) Software interrupt is available just by writing Break(BRK) instruction. The values of PC and PSW is stacked by BRK instruction and then B flag of PSW is set and I flag is reset. SEP. 2004 Ver 1.01 HMS87C5216 Flag change by BRK execution PSW N V G B H I Z C set PSW N V G 1 H 0 reset Z C (Right after BRK execution) Interrupt vector of BRK instruction is shared by vector of Table Call (TCALL0). When both instruction of BRK and TCALL0 are used, as shown in Figure 13-4each processing routine is judged by contents of B flag. There is no instruction to reset directly B flag. B flag 1 BRK or TCALL0 BRK INTERRUPT ROUTINE 0 TCALL0 ROUTINE RETI RET Figure 13-4 Execution of BRK or TCALL0 13.6 MULTIPLE INTERRUPT If there is an interrupt, Interrupt Mask Enable Flag is automatically cleared before entering the Interrupt Service Routine. After then, no interrupt is accepted. If EI instruction is executed, interrupt mask enable bit becomes 1, and each enable bit can accept interrupt request. When two or more interrupts are generated simultaneously, the highest priority interrupt set by Interrupt Mode Register is accepted. 13.7 Key Scan Input Processing (1) Standby Mode Release Register (SMRR) Key Scan Interrupt is generated by detecting low or high Input from each Input pin (R0, R1) is one of the sources which release standby (SLEEP, STOP) mode. Key Scan ports are all 16bit which are controlled by Standby Mode Release Register (SMRR0, SMRR1). Key Input is considered as Interrupt, therefore, KSCNE bit of IEHN should be set for correct interrupt ex- SEP. 2004 Ver 1.01 HMS87C5216 ecuting, SLEEP mode and STOP mode, the rest of executing is the same as that of external Interrupt. Each SMRR Register bit is allowed for each port (for Bit= 0, no Key Input, for Bit= 1, Key Input available). At reset, SMRR becomes 00 h. So, there is no Key Input source. 7 0 W <00DC h> SMRR0 R00 R01 . . . R07 R0 port Selection Logic Internal Key Scan Interrupt 7 0 W <00DD h> SMRR1 R10 R11 . . . R17 R0 port Selection Logic Figure 13-5 Key Scan Block 7 SMRR0 KR07 KR06 KR05 SMRR0 Register KR04 KR03 KR02 KR01 0 KR00 W <00DC h> 7 SMRR1 KR17 KR16 KR15 SMRR1 Register KR14 KR13 KR12 KR11 0 KR10 W <00DD h> SEP. 2004 Ver 1.01 HMS87C5216 SMRR0 KR07 0 1 KR06 0 1 KR05 0 1 KR04 0 1 KR03 0 1 KR02 0 1 KR01 0 1 KR00 0 1 SMRR1 KR17 0 1 KR16 0 1 KR15 0 1 KR14 0 1 KR13 0 1 KR12 0 1 KR11 0 1 KR10 0 1 Key Input Selection no select select no select select no select select no select select no select select no select select no select select no select select (2) Standby Release Level Control Register (SRLC) Standby release level control register (SRLC) can select the key scan input level L or H for standby release by each bit pin (R0, R1). Standby release level control register (SRLC) is writeonly register and initialized as 00 h in reset state. 7 SRLC0 KLR07 KLR06 KLR05 SRLC0 Register KLR04 KLR03 KLR02 KLR01 0 KLR00 W <00F6 h> 7 SRLC1 KLR17 KLR16 KLR15 SRLC1 Register KLR14 KLR13 KLR12 KLR11 0 KLR10 W <00F7 h> SEP. 2004 Ver 1.01 HMS87C5216 SRLC0 KLR07 0 1 KLR06 0 1 KLR05 0 1 KLR04 0 1 KLR03 0 1 KLR02 0 1 KLR01 0 1 KLR00 0 1 SRLC1 KLR17 0 1 KLR16 0 1 KLR15 0 1 KLR14 0 1 KLR13 0 1 KLR12 0 1 KLR11 0 1 KLR10 0 1 Key Input Level Low High Low High Low High Low High Low High Low High Low High Low High SEP. 2004 Ver 1.01 HMS87C5216 14. WATCH DOG TIMER Watch Dog Timer (WDT) consists of 6-bit binary counter, 6-bit comparator, and Watch Dog Timer Register (WDTR). 0 IFBIT WDT0 WDT1 WDT2 WDT3 WDT4 5 CLR WDT5 To Reset circuit WDTON 6BIT COMPARATOR IF WDT WDTR WDTR0 0 WDTR1 WDTR2 WDTR3 WDTR4 WDTR5 WDTCL 6 W <00C8 h> Internal Data Bus Figure 14-1 Block diagram of Watch Dog Timer 14.1 Control of WDT Watch Dog Timer can be used 6-bit general Timer or specific Watch dog timer by setting bit5 (WDTON) of Clock Control Register (CKCTLR). 7 CKCTLR Clock Control Register WDTON ENPCK BTCL BTS2 BTS1 0 BTS0 W <00C7 h> - WDTON 0 1 Watch Dog Timer Function Control 6-bit Timer Watch Dog Timer By assigning bit6(WDTCL) of WDTR, 6-bit counter can be cleared. SEP. 2004 Ver 1.01 HMS87C5216 7 WDTR Watch DOG Timer Register WDTCL WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 0 WDTR0 W <00C8 h> - Determine Interval of IFWDT Interval of IFWDT = Value of WDTR x Interval of IFBIT WDTCL 0 1 Watch Dog Timer Operation free-run Automatically cleared, after one machine cycle 14.2 WDT Interrupt Interval WDT Interrupt (IFWDT) interval is determined by the interrupt IFBIT interval of Basic Interval Timer and the value of WDT Register. -Interval of IFWDT = (IFBIT interval) * (WDTR value) -Interval of IFWDT : 512 us * 1 = 512 us (MIN>) -65,536us * 63 = 4,128,768 us (MAX>) As IFBIT (Basic Interval Timer Interrupt Request) is used for input clock of WDT, Input clock cycle is possible from 512 us to 65,536 us by BTS. (at fex = 4MHz) *At Hardware reset time ,WDT starts automatically. Therefore, the user must select the CKCTLR, WDTR before WDT overflow. -Reset WDTR value = 0F h,15 -interval of WDT = 65,536 * 15 = 983040 us (about 1second ) 7 CKCTLR Clock Control Register WDTON ENPCK BTCL BTS2 BTS1 0 BTS0 W <00C7 h> - BTS2 0 0 0 0 1 1 1 1 BTS1 0 0 1 1 0 0 1 1 BTS0 0 1 0 1 0 1 0 1 WDT Input clock 512 us 1,024 us 2,048 us 4,096 us 8,192 us 16,384 us 32,768 us 65,536 us Max. Interval of WDT Output (*note1) 32,756 us 64,512 us 129,024 us 258,048 us 516,096 us 1,032,192 us 2,064,384 us 4,128,768 us Note: When WDTR Register value is 63 (3F h) (Caution) : Do not use 0 for WDTR Register value. Device come into the reset state by WDT SEP. 2004 Ver 1.01 HMS87C5216 15. STANDBY FUNCTION To save power consumption, there is STOP modes. In this modes, the execution of program stops. 15.1 Sleep Mode SLEEP mode can be entered by setting the bit of SLEEP mode register (SLPM). In the mode, CPU clock stops but oscillator keeps running. B.I.T and a part of peripheral hardware execute, but prescaleris output which provide clock to peripherals can be stopped by program. (Except, PS10 canit stopped.) In SLEEP mode, more consuming power can be saved by not using other peripheral hardware except for B.I.T. By setting ENPCK (peripheral clock control bit) of CKCTLR (clock control register) to 0, peripheral hardware halted, and SLEEP mode is entered. To release SLEEP mode by BITR (basic interval timer interrupt), bit10 of prescaler should be selected as B.I.T input clock before entering SLEEP mode. NOP instruction should be follows setting of SLEEP mode for rising precharge time of data bus line. (ex) setting of SLEEP mode : set the bit of SLEEP ; mode register (SLPM) NOP : NOP instruction 7 SLPM SLEEP MODE CONTROL Register - 0 SLPM0 W <00F0 h> - - - - - SLPM0 0 1 condition sleep mode release sleep mode 7 CKCTLR Colck Control Register WDTON ENPCK BTCL BTS2 BTS1 0 BTS0 W <00C8 h> - ENCPK 0 1 Peripheral Clock stopped provided 15.2 STOP MODE STOP mode can be entered by STOP instruction during program. In STOP mode, oscillator is stopped to make all clocks stop, which leads to less power consumption. All registers and RAM data are preserved. NOP instruction should be follows STOP instruction for rising precharge time of Data Bus line. (ex) STOP NOP : STOP instruction execution : NOP instruction SEP. 2004 Ver 1.01 HMS87C5216 OSC. Circuit Clock Pulse GEN CLR CPU Clock MUX Basic Interval Timer Prescaler CLR CLR B.I.T 7 STOP S R Q S R Q Control Signal Overflow Detection Release Signal From Interrupt Circuit RESET Figure 15-1 Block Diagram of Standby Circuit Prescaler ENPCK PS10 Selector Basic Interval Timer Peripheral Figure 15-2 ENPCK and Basic Interval Timer Clock SEP. 2004 Ver 1.01 HMS87C5216 15.3 STANDBY MODE RELEASE Release of STANDBY mode is executed by RESET input and Interrupt signal. Register value is defined when Reset. When there is a release signal of STOP mode (Interrupt, RESET input), the instruction execution starts after stabilization oscillation time is set by value of BTS2 ~ BTS0 and set ENPCK to 1. Release Signal RESET KSCN (key input) INT1 , INT2 B.I.T SLEEP O O O O STOP O O O X Table 15-1 Standby Mode Register Release Factor Release Method RESET KSCN (key input) By RESET Pin = Low level, Standby mode is release and system is initialized Standby mode is released by low input of selected pin by key scan Input (SMRR0, SMRR1) In case of interrupt mask enable flag = 0, program executes just after standby instruction, if flag = 1, enters each interrupt service routine. When external interrupt (INT1, INT2) enable flag is 1, standby mode is released at the rising edge of each terminal. When Standby mode is released at interrupt. Mask Enable flag = 0, program executes from the next instruction of standby instruction. When 1, enters each interrupt service routine. When B.I.T is executed only by bit10 of prescaler (PS10), SLEEP mode can be release. Interrupt release SLEEP mode, when BIT interrupt enable flag is 1. When standby mode is released at interrupt. Mask enable flag = 0, program executes from the next instruction of SLEEP instruction. When 1, enters each interrupt service routine. INT1 INT2 Basic Interval Timer (IFBIT) Table 15-2 Standby Mode Release SEP. 2004 Ver 1.01 HMS87C5216 [ SLEEP MODE ] Xin SLEEP command SLEEP Mode release by interrupt RESET Longer than 2 machine cycle [ STOP MODE ] clock STOP Mode Stable OSC. time release by interrupt Program Setting Time by CKCTLR RESET Longer than stable OSC. Time Figure 15-3 Release Timing of Standby Mode 15.4 RELEASE OPERATION OF STANDBY MODE After standby mode is released, the operation begins according to content of related interrupt register just before standby mode start (Figure 15-4) Note: When STOP instruction is used, B.I.T should guarantee the stabilization oscillation time. Thus, just before entering STOP mode, clock of bit10 (PS10) of prescaler is selected or peripheral hardware clock control bit (ENPCK) to 1, Therefore the clock necessary for stabilization oscillation time should be input into B.I.T. otherwise, standby mode is released by reset signal. In case of interrupt request flag and interrupt enable flag are both 1, standby mode is not entered. (1) Interrupt Enable Flag(I) of PSW = 0 Release by only interrupt which interrupt enable flag = 1, and starts to execute from next to standby instruction (SLEEP or STOP). (2) Interrupt Enable Flag(I) of PSW = 1 Released by only interrupt which each interrupt enable flag = 1, and jump to the relevant interrupt service routine. SEP. 2004 Ver 1.01 HMS87C5216 STOP Command Standby Mode Interrupt Request GEN. 0 IE Flag 1 Standby Mode Release PSW IE Flag 1 Interrupt Service Routine 0 Standby Next Command Execution Figure 15-4 Standby Mode Release Flow Internal circuit Oscillator Internal CPU clock Register RAM I/O port Prescaler Basic Interval Timer Watch Dog Timer Timer Address Bus, Data Bus SLEEP mode Active Stop Retained Retained Retained Active PS10 selected : Active Others : Stop Stop Stop Retained Stop Stop STOP mode Retained Retained Retained Retained Stop Stop Stop Retained Table 15-1 Operation State in Standby Mode SEP. 2004 Ver 1.01 HMS87C5216 16. OSCILLATION CIRCUIT Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Fig. 4.2-(a) shows circuit diagrams using a crystal (or ceramic) oscillator. As shown in the diagram, oscillation circuits can be constructed by connecting a oscillator between Xout and Xin. Clock from oscillation circuit makes CPU clock via clock pulse generator, and then enters prescaler to make peripheral hardware clock. Alternately, the oscillator may be driven from an external source as shown is Fig. 4.2.(b). In the Standby (STOP) mode, oscillatiion stop, Xout state goes to HIigh, Xin state goes to Low, and built-in feed back resistor is disabled. (a) External Crystal (Ceramic) oscillator circuit Cout Xout Xin Cin (b) External clock input circuit Xout Xin External clock Figure 16-1 Oscillator configurations * Recommendable resonator Frequency Resonator Maker CQ Part Name ZTA4.00MG FCR4.0MC5 FCR4.0M5 CCR4.0MC3 Load Capacitor Cin=Cout=30pF Cin=Cout=open Cin=Cout=33pF Operating Voltage 2.2 ~ 4.0V 2.2 ~ 4.0V 2.2 ~ 4.0V 2.2 ~ 4.0V 4.0 MHz TDK TDK TDK * MC type is building in load capacitior.CCR type is chip type. SEP. 2004 Ver 1.01 HMS87C5216 17. RESET FUNCTION 17.1 EXTERNAL RESET The RESET pin should be held at low for at least 2machine cycles with the power supply voltage within the operating voltage range and must be connected 0.1uF capacitor for stable system initialization. The RESET pin contains a Schmitt trigger with an internal pull-up resistor. RESET 0.1 uF Capacitor Figure 17-1 17.2 POWER ON RESET Power On Reset circuit automatically detects the rise of power voltage (the rising time should be within 50ms) the power voltage reaches a certain level, RESET terminal is maintained at L Level until a crystal ceramic oscillator oscillates stably. After power applies and starting of oscillation, this reset state is maintained for about oscillation cycle of 219 (about 65.5ms : at 4MHz).The execution of built-in Power On Reset circuit is as follows : (1) Latch the pulse from Power On Detection Pulse Generator circuit, and reset Prescaler, B.I.T and B.I.T Overflow detection circuit. (2) Once B.I.T Overflow detection circuit is reset. Then, Prescaler starts to count. (3) Prescaler output is inputted into B.I.T and PS10 of Prescaler output is automatically selected. If overflow of B.I.T is detected, Overflow detection circuit is set. (4) Reset circuit generates maximum period of reset pulse from Prescaler and B.I.T. Internal IC VDD RESET 0.1uF Internal Reset Power On DET Pulse GEN. VSS XTAL OSC. CLR Prescaler PS10 CLR Basic Interval Tiemr MSB CLR Basic Interval Tiemr Figure 17-2 Block Diagram of Power On Reset Circuit Note: Notice ; When Power On Reset, oscillator stabiliza- tion time doesnt include OSC. Start time. SEP. 2004 Ver 1.01 HMS87C5216 VDD PRESCALER COUNT START OSC. START TIMING Figure 17-3 Oscillator stabilization diagram RESET INTERNAL RESET ADDR. BUS SP SP-1 SP-2 FFFE FFFF NEW PC INTERNAL DATA BUS FE LSB MSB VECTOR VECTOR Figure 17-4 Reset Timing by Diagram 17.3 Low Voltage Detection Mode (1) Low voltage detection condition An on board voltage comparator checks that VDD is at the required level to ensure correct operation of the device. If VDD is below a certain level, Low voltage detector forces the device into low voltage detection mode. capacitor is worn out. In this mode, all port can be selected with Pull-up resistor by Mask option. If there is no information on the Mask option sheet ,the default pull up option (all port connect to pull-up resistor ) is selected. (3) Release of Low Voltage Detection Mode Reset signal result from new battery(normally 3V) wakes the low voltage detection mode and come into normal reset state. It depends on user whether to execute RAM clear routine or not. (2) Low Voltage Detection Mode There is no power consumption except stop current, stop mode release function is disabled. All I/O port is configured as input mode and Data memory is retained until voltage through external SEP. 2004 Ver 1.01 HMS87C5216 Low Voltage (V) 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 10 20 30 40 50 60 70 Temperature() Figure 17-5 Low Voltage vs Temperature (4) SRAM BACK-UP after Low Voltage Detection. 3.0V about hours depend on Vcc-Gnd Capacitor MCU OPR. Voltage Low Voltage Detection point 1.8V(TYP) ( 20) Power On Reset ( SRAM retention) 0.7V(VRET) 0V * SRAM Data Backup * The operation after Low voltage detection Interrupt : disable User Stop release : disable Removes All I/O port : input Mode Batteries Remout port : Low Level OSC : STOP All I/O port pull-up ON (Mask Option ) SRAM Data retention Figure 17-6 Low Voltage Detection and Protection Power On Reset ( SRAM unstable ) User Replace Batteries SEP. 2004 Ver 1.01 HMS87C5216 (5) S/W flow chart example after Reset using SRAM Back-up RESET Stack Pointer initialize Check the SRAM value (RAM Pattern, Check sum..) SRAM DATA IS VALID? Y Use saved SRAM value N Clear All Ram area Figure 17-7 S/W Flow Chart Example for SRAM Back- up 17.4 Low Voltage Indicator Register (LVIR) Low Voltage Indication Register (LVIR) is read only Register. It is useful to display the consumption of Batteries. If VDD power level is below a cirtain level which is higher than low voltage detection level ( refer to Figure 17-6 ) , The bit of LVIR register could be set according to the VDD level sequentially. The VDD dection levels for Indication are two , that is , Bit1 and Bit0 of LVIR Register. The detection level of Bit0 is higer than Bit1. bit LVIR initial value R/W 7 - 6 - 5 - 4 - 3 - 2 - 1 LVIR1 0 R 0 LVIR0 0 R <00EF h> SEP. 2004 Ver 1.01 HMS87C5216 18. CLOCK GENERATOR Clock generating circuit consists of Clock Pulse Generator (C.P.G), Prescaler, Basic Interval Timer (B.I.T) and Watch Dog Timer. The clock applied to the Xin pin divided by two is used as the internal system clock. OSC Circuit fex C.P.G fcpu Internal System Clock PRESCALER IFBIT PS1 ENPCK 8 MUX B.I.T (8) WDT (6) 0 7 0 5 WDTCL BTCL 3 Peripheral COMPARATOR WDTON 6 WDTR 0 5 6 6 CKCTLR 0 1 2 3 4 5 Internal Data Bus Figure 18-1 Block Diagram of Clock Generator Prescaler consists of 12-bit binary counter. The clock supplied from oscillation circuit is input to prescaler (fex). The divided output from each bit of prescaler is provided to peripheral hardware. fex PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 ENPCK fcpu PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 Figure 18-2 Block diagram of Prescaler 9 IFWDT To Reset Circuit PS9 PS10 PS11 PS12 B.I.T PS9 PS10 PS11 PS12 Peripheral SEP. 2004 Ver 1.01 HMS87C5216 fex (MHz) ps 0 ps 1 ps 2 ps 3 ps 4 ps 5 ps 6 ps 7 ps 8 ps 9 ps 10 ps 11 ps 12 4 MHz frequency 4 MHz 2 MHz 1 MHz 500 KHz 250 KHz 125 KHz 62.5 KHz 31.25 KHz 15.63 KHz 7.183 KHz 3.906 KHz 1.953 KHz 0.976 KHz period 250 ns 500 ns 1 us 2 us 4 us 8 us 16 us 32 us 64 us 128 us 256 us 512 us 1024 us frequency 2 MHz 1 MHz 500 KHz 250 KHz 125 KHz 62.5 KHz 31.25 KHz 15.63 KHz 7.183 KHz 3.906 KHz 1.953 KHz 0.976 KHz 0.488 KHz 2 MHz period 500 ns 1 us 2 us 4 us 8 us 16 us 32 us 64 us 128 us 256 us 512 us 1024 us 2048 us Table 18-1 ps output perio Basic Interval Timer The HMS87C5216 and GMS81C1408 has one 8-bit Basic Inter(only fxin/2048) and Timer0. val Timer that is free-run, can not stop. Block diagram is shown If the STOP instruction executed after writing "1" to bit RCWDT in Figure 18-3.The 8-bit Basic interval timer register (BITR) is of CKCTLR, it goes into the internal RC oscillated watchdog timincreased every internal count pulse which is divided by prescaler mode. In this mode, all of the block is halted except the internal er. Since prescaler has divided ratio by 8 to 1024, the count rate RC oscillator, Basic Interval Timer and Watchdog Timer. More is 1/8 to 1/1024 of the oscillator frequency. As the count overdetail informations are explained in Power Saving Function. The flows from FFH to 00H, this overflow causes to generate the Basic bit WDTON decides Watchdog Timer or the normal 7-bit timer interval timer interrupt. The BITF is interrupt request flag of Basic interval timer. Note: All control bits of Basic interval timer are in CKCTLR When write "1" to bit BTCL of CKCTLR, BITR register is register which is located at same address of BITR (address cleared to "0" and restart to count-up. The bit BTCL becomes "0" ECH). Address ECH is read as BITR, written to CKCTLR. after one machine cycle by hardware. Therefore, the CKCTLR can not be accessed by bit manipulation instruction. If the STOP instruction executed after writing "1" to bit WAKEUP of CKCTLR, it goes into the wake-up timer mode. In this mode, all of the block is halted except the oscillator, prescaler . RCWDT BTS[2:0] fxin /8 / 16 / 32 / 64 / 128 / 256 / 512 / 1024 3 BTCL Clear To Watchdog Timer 8 MUX 0 BITR (8BIT) 1 BITIF Basic Interval Timer Interrupt Internal RC OSC Figure 18-3 Block Diagram of Basic Interval Timer SEP. 2004 Ver 1.01 HMS87C5216 Clock Control Register CKCTLR - WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0 ADDRESS : ECH RESET VALUE : -0010111 Bit Manipulation Not Available Basic Interval Timer Clock Selection Symbol WAKEUP RCWDT WDTON BTCL Function Description 1 : Enables Wake-up Timer 0 : Disables Wake-up Timer 1 : Enables Internal RC Watchdog Timer 0 : Disables Internal RC Watchdog Time 1 : Enables Watchdog Timer 0 : Operates as a 7-bit Timer 1 : BITR is cleared and BTCL becomes "0" automatically after one machine cycle, and BITR continue to count-up 000 : fxin / 8 001 : fxin / 16 010 : fxin / 32 011 : fxin / 64 100 : fxin / 128 101 : fxin / 256 110 : fxin / 512 111 : fxin / 1024 Figure 18-4 CKCTLR: Clock Control Register SEP. 2004 Ver 1.01 HMS87C5216 19. ANALOG TO DIGITAL CONVERTER The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit digital value. The A/ D module has eight analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is VDD. The A/D module has two registers which are the control register ADMR and A/D result register ADDR. The ADMR register, shown in Figure 19-2, controls the operation of the A/D converter module. The port pins can be configure as analog inputs or digital I/O. To use analog inputs, each port is assigned analog input port by setting the bit ANSEL[7:0] in RAFUNC register. And selected the corresponding channel to be converted by setting ADS[2:0]. The processing of conversion is start when the start bit ADST is set to "1". After one cycle, it is cleared by hardware. The register ADCR contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADCR, the A/ D conversion status bit ADSF is set to "1", and the A/D interrupt flag ADIF is set. The block diagram of the A/D module is shown in Figure 19-1. The A/D status bit ADSF is set automatically when A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes maximum 30 uS (at fxin=4 MHz). ADAN[1:0] A/D Result Register ADDR(8-bit) ADDRESS : EDH RESET VALUE : Undefined R1[7]/AN3 ADEN R1[6]/AN2 ADEN R1[5]/AN1 ADEN R1[4]/AN0 ADEN 11 Sample & Hold 10 S/H Successive Approximation Circuit ADIF A/D Interrupt 01 00 Resistor Ladder Circuit AVDD ADEN Figure 19-1 A/D Converter Block Diagram SEP. 2004 Ver 1.01 HMS87C5216 A/D Control Register ADMR - ANEN ADAN3 ADAN2 ADAN1 ADAN0 ADST ADF ADDRESS : F4H RESET VALUE : --000001 Analog Channel Select 0000 : Channel 0 (R1[4]/AN0) 0001 : Channel 1 (R1[5]/AN1) 0010 : Channel 2 (R1[6]/AN2) 0011 : Channel 3 (R1[7]/AN3) A/D Status bit 0 : A/D Conversion is in process 1 : A/D Conversion is completed A/D Start bit 1 : A/D Conversion is started After 1 cycle, cleared to "0" 0 : Bit force to zero A/D Enable bit 1 : A/D Conversion is enable 0 : A/D Converter module shut off and consumes no operation current A/D Result Data Register ADCR ADCR7 ADCR6 ADCR5 ADCR4 ADCR3 ADCR2 ADCR1 ADCR0 ADDRESS : F5H RESET VALUE : Undefined Figure 19-2 A/D Converter Registers A/D Converter Cautions ENABLE A/D CONVERTER (1) Input range of AN0 to AN3 The input voltage of AN0 to AN3 should be within the specification range. In particular, if a voltage above VDD or below Vss is input (even if within the absolute maximum rating range), the conversion value for that channel can not be indeterminate. The conversion values of the other channels may also be affected. (2) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on pins VDD and AN0 to AN3. Since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 19-4 in order to reduce noise. A/D INPUT CHANNEL SELECT ANALOG REFERENCE SELECT A/D START (ADST = 1) NOP Analog Input 100~1000pF AN0~AN3 ADSF = 1 NO YES READ ADCR Figure 19-4 Analog Input Pin Connecting Capacitor (3) Pins AN0/R1[4] and AN1/R1[5] to AN3/R1[7] Figure 19-3 A/D Converter Operation Flow The analog input pins AN0 to AN3 also function as input/output port (PORT R1 ) pins. When A/D conversion is performed with SEP. 2004 Ver 1.01 HMS87C5216 any of pins AN0 to AN3 selected, be sure not to execute a PORT input instruction while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion. SEP. 2004 Ver 1.01 HMS87C5216 SEP. 2004 Ver 1.01 |
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